Node-Level Performance Engineering

Enterprises & SME Research & Science
Node-Level Performance Engineering


This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy, apply it to different algorithms from computational science, and also show how an awareness of the performance features of an application may lead to notable reductions in power consumption.This course provides scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.


First day:

09:00 - 09:30 local registration
09:30 - 13:00 lectures (with breaks: 10:30-10:45 & 11:45-12:00)
13:00 - 14:00 lunch break
14:00 - 17:00 lectures  (with breaks: 15:10-15:25)

Second day:

09:00 - 13:00 lectures (with breaks: 10:15-10:30 & 11:45-12:00)
13:00 - 14:00 lunch break
14:00 - 17:00 lectures  (with breaks: 15:10-15:25)

Detailed Program


  • Our approach to performance engineering
  • Basic architecture of multicore systems: threads, cores, caches, sockets, memory
  • The important role of system topology

Tools: topology & affinity in multicore environments

  • Overview
  • likwid-topology and likwid-pin

Microbenchmarking for architectural exploration

  • Properties of data paths in the memory hierarchy
  • Bottlenecks
  • OpenMP barrier overhead

Roofline model: basics

  • Model assumptions and construction
  • Simple examples
  • Limitations of the Roofline model

Tools: hardware performance counters

  • Why hardware performance counters?
  • likwid-perfctr
  • Validating performance models

Roofline case studies

  • Dense matrix-vector multiplication
  • Sparse matrix-vector multiplication
  • Jacobi (stencil) smoother
  • Optimal use of parallel resources
  • Single Instruction Multiple Data (SIMD)
  • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
  • Simultaneous Multi-Threading (SMT)

Extending Roofline: The ECM performance model

Optional: Pattern-based performance engineering


Participants must have basic knowledge in programming with Fortran or C, and basic OpenMP.


Dr. habil. Georg HagerDr.-Ing. Jan Eitzinger (vormals Treibig), and Prof. Dr. Gerhard Wellein (RRZE/HPC, Uni. Erlangen)


Before the course, the course material and an updated agenda will be available here.
An older version of this course with most of the material (including the audio information) can also be viewed in the ONLINE Parallel Programming Workshop.


Late registration is still possible via the online registration form.

Extended Deadline with Late Registration

for registration is June 12, 2016 (extended deadline).
Late registrations after the deadline are still possible but maybe with reduced quality of the handouts.


Members of German universities and public research institutes: none.
Members of universities and public research institutes within Europe or PRACE: none.
Members of other universities and public research institutes: 120 EUR.
Others: 400 EUR.
(includes coffee breaks)


Travel Information and Accommodation

see our How to find us page.


HLRS is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in Feb. 2012. The mandate for the PATCs is as follows: "The PRACE Advanced Training Centres will serve as European hubs of advanced, world-class training for researchers working in the computational sciences." (see D3.2.3)
This course is a PATC course, see also the PRACE Training Portal and Events. For participants from public research institutions in PRACE countries, the course fee is sponsored through the PRACE PATC program.

HLRS is also member of the Baden-Württemberg initiative bwHPC-C5.
This course is also provided within the framework of the bwHPC-C5 user Support.

Local Organizer

Rolf Rabenseifner phone 0711 685 65530,
Joerg Hertzer phone 0711 685 65932,