HLRS Scientists Win Research Poster Award at ISC26

The investigators tested the suitability of the Cerebras Wafer-Scale Engine for accelerating traditional simulation workflows.

Daniel Renschler and Jonathan Schäfer, two student researchers at the High-Performance Computing Center Stuttgart (HLRS), accepted the third prize in the Best Poster Award competition at the ISC High Performance Conference in Hamburg, Germany.

Their poster, titled SpMV for the Cerebras Wafer-Scale Engine reports on the successful implementation of a sparse matrix-vector product (SpMV) method on an experimental, massively parallel computing accelerator. The Wafer-Scale Engine (WSE), manufactured by California-based startup Cerebras, holds up to 900,000 compute cores on a single, large-scale chip. Developed for artificial intelligence training and inference applications, the WSE's unique architecture offers dramatically faster speeds in comparison to conventional AI processors.

Published

Jun 24, 2026

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In today's current generation of high-performance computing systems, processors that were originally used for artificial intelligence applications have increasingly been repurposed to accelerate traditional simulation workloads, enable hybrid workflows that combine simulation and data-driven methods, and run data-intensive tasks that can be managed faster on AI-optimized processors. Renschler, Schäfer and his colleagues wanted to understand whether the WSE could also be used in this way.

In their tests they focused on SpMV, a computational method that is commonly used in classical applications for simulation such as finite element analysis and computational fluid dynamics. Renschler and Schäfer used the Wafer-Scale Engine to accelerate a highly parallelized component of a typical simulation workflow that includes this method. They also performed weak- and strong-scaling experiments, revealing bottlenecks that affected application performance. This enabled the investigators to suggest optimization strategies that could improve performance of SpMV methods on the WSE in the future.

The research was conducted within the context of the HLRS Future Computing Group, led by Dr. Johannes Gebert, a multidisciplinary research team within HLRS that tests and evaluates emerging hardware concepts and their suitability for typical high-performance computing applications.

Renschler, Schäfer and Gebert conducted this experiment together with Mark Parsons, director of EPCC in Edinburgh.

— Christopher Williams