Most current HPC systems are heterogenous and use accelerators. oneAPI is a standardized and portable programming model adapted to heterougenuous computing. In this course we will provide an introduction to Intel's oneAPI implementation, which supports two portable methods of heterougenuous computing: Data Parallel C++ (DPC) with SYCL and OpenMP for C, C++, and Fortran. Both are portable on any Intel CPU and Intel based accelerator. The course will give an introduction in these two programming methods, Intel's libraries like oneMKL and tools for performance analysis, profiling, and debugging. Further an introduction to Intel's DPC compatibility Tool to facilitate code migration from CUDA to SYCL and to Intel's MPI implementation support with GPU awereness completes the program. Insights into migrating an application to oneAPI/SYCL will be provided by GROMACS developers.
Online course Organizer: HLRS, University of Stuttgart, Germany
26. Okt 2022
28. Okt 2022
Programming Languages for Scientific Computing
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Good knowlegde any of C/C++/Fortran and familiarity with usual OpenMP programming is sufficient for the OpenMP part. For Data Parallel C++/SYCL knowlegde of C++11 or later is recommended (C++17 very much faciliates SYCL2020 programming).
Learn more about course curricula and content levels.
Intel staff and GROMACS developers.
After this course, participants will:
The preliminary agenda is as follows. All times are CEST.
Welcome and Introduction to Day 1
oneAPI – Introduction to a new Development Environment - Concept and oneAPI Standardization initiative - Intel’s Tools Implementation – Intel oneAPI Toolkits and libs - Transition from Intel Parallel Studio XE to Intel oneAPI toolkits
Introduction to the DevCloud - Purpose: Demoing, testing and porting applications - Hardware and Software offerings - How to onboard & how to get an DevCloud account
Direct programming with oneAPI Compilers (Part 1) – with Demos - Intro to heterogenous programming model with SYCL 2020 - SYCL features and examples o “Hello World” Example o Device Selection o Execution Model
Direct programming with oneAPI Compilers (Part 2) – with Demos o Compilation and Execution Flow o Memory Model; Buffers, Unified Shared Memory (USM) o Performance optimizations with SYCL features
Intel OpenMP for Offloading – with Demos - Parallelizing heterogenous applications with OpenMP 5.1 - Mixing of OpenMP and SYCL
Intel oneAPI libraries (oneMKL) for HPC - with demos - Performance optimized libraries for numerical simulations and other purposes
Intel Debugging Tools for heterogenous programming ( CPU, GPU ) - with demos
Open Source Compatibility tool for porting purposes (SYCLomatic) - with demo - Migration Cuda based GPU Applications to SYCL
Dynamic Debugging with Intel Inspector - with demos - Identifying Memory and Threading Errors (Data Races and Deadlocks)
Application profiling for heterogenous hardware - Demos - Profiling Tools Interfaces for GPU - Open Source lightweight Tools - Profile heterogenous SYCL/OpenMP Workloads with Intel VTune Profiler - Share experiences/key findings with Gromacs related porting and optimization efforts
Application profiling for heterogenous hardware - Demos - Estimate performance potential gains with Offload Advisor (CPU -> HW Accelerator) - Analyse heterogenous SYCL/OpenMP Workloads with Intel Advisor and Roofline analysis
A 3rd Party oneAPI Case Study: GROMACS - A Molecular Dynamics Engine - Heterogenous Design consideration, alternatives and comparisons - Real Scheduling - SYCL - oneAPI and other Implementations - SYCL in GROAMCS 2022
Programming for Distributed HPC Systems using Intel MPI
- Questions and Answers - Wrap up
In the course only demonstrations will be shown. However, we will also show how to access Intel's DevCloud where participants can explore and work on the examples given themself in the afternoon.
Register via the button at the top of this page.
Registration closes on September 27, 2022.
This course is free of charge.
Our course fee includes coffee breaks (in classroom courses only).
Tobias Haas phone 0711 685 87223, tobias.haas(at)hlrs.de
HLRS is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in Feb. 2012.
HLRS is also member of the Baden-Württemberg initiative bwHPC.
This course is not part of the PATC curriculum and is not sponsored by the PATC program.
See the training overview and the Supercomputing Academy pages.
Oktober 24, 2022
Oktober 24, 2022
Hybrid Event - Stuttgart, Germany
Online by VSC Vienna
Online by JSC
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Nobelstraße 19, 70569 Stuttgart, Deutschland
Ihr Weg zu uns
+49 (0) 711 / 685-87 209
Als Mitglied des Gauss Centre for Supercomputing ist das HLRS eines der drei Bundeshöchstleistungsrechenzentren.
Das HLRS ist eine zentrale Einrichtung der Universität Stuttgart.