Introduction to NEC SX-Aurora TSUBASA vector platform

This two day training will introduce the SX-Aurora TSUBASA installation at HLRS. The architecture will be presented and compared to other architectures and SX-ACE, an introduction to programming of vector CPUs will be given and vectorization will be discussed on examples. Usage of the system at HLRS will be demonstrated. In addition, an introduction to ML/DL solutions using the NEC SX-Aurora TSUBASA cards will be given. Participants can apply for test accounts to test their own code on the SX-Aurora TSUBASA after the course.

Veranstaltungsort

Online course
Organizer: HLRS, University of Stuttgart, Germany

Veranstaltungsbeginn

01. Dez 2022
08:45

Verstaltungsende

02. Dez 2022
13:30

Sprache

Englisch

Einstiegslevel

Basic

Themenbereiche

Parallel Programming

Themen

Artificial Intelligence

Big Data

Code Optimization

Deep Learning

Machine Learning

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Prerequisites and content levels

Prerequisites

Knowledge of one C/C++/Fortran. For the AI part, knowledge of Python might be a plus.

Content levels

Intermediate: 8 hours.

Learn more about course curricula and content levels.

Instructors

Holger Berger, Erich Focht, and Patrick Lipka from NEC Deutschland GmbH

Learning outcomes

After this course, participants will: 

  • be familiar with the vector architecture
  • have experience with compilers, performance analysis and debugging for the SX-Aurora TSUBASA
  • have an overview over AI/ML/DL support for the SX-Aurora TSUBASA

Agenda

All times are local times in the central European time zone (Berlin). The preliminary schedule is as follows.

Day 1

08:45 - 09:00 Drop in to Zoom
09:00 - 13:30 Lectures and exercises

Day 2

08:45 - 09:00 Drop in to Zoom
09:00 - 13:30 Lectures and exercises (Advanced topics, AI/ML/DL support, hybrid MPI)

Topics on the two days include

  • architecture overview and comparison
  • what is vectorization
  • compilers and options
  • performance tools
  • debugging
  • listing files
  • loop optimization techniques
  • batch system usage
  • AI/DL/ML on the SX-Aurora TSUBASA
  • hybrid MPI

Registration information

Register via the button at the top of this page (will be available soon).

Registration closes on November 17, 2022 (extended registration phase).

Late registrations after that date are still possible according to the course capacity, possibly with reduced quality of service.

Fees

This course is free of charge.

Contact

Tobias Haas phone 0711 685 87223, tobias.haas(at)hlrs.de
Khatuna Kakhiani phone 0711 685 65796, kakhiani(at)hlrs.de

PRACE PATC and bwHPC

HLRS is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in Feb. 2012.

HLRS is also member of the Baden-Württemberg initiative bwHPC.

This course is not part of the PATC curriculum and is not sponsored by the PATC program.

Further courses

See the training overview and the Supercomputing Academy pages.

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