Node-Level Performance Engineering

This course will be provided as ONLINE course (using Zoom).

This course covers performance engineering approaches on the compute node level. Even application developers who are fluent in OpenMP and MPI often lack a good grasp of how much performance could at best be achieved by their code. This is because parallelism takes us only half the way to good performance. Even worse, slow serial code tends to scale very well, hiding the fact that resources are wasted. This course conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. We introduce the basic architectural features and bottlenecks of modern processors and compute nodes. Pipelining, SIMD, superscalarity, caches, memory interfaces, ccNUMA, etc., are covered. A cornerstone of node-level performance analysis is the Roofline model, which is introduced in due detail and applied to various examples from computational science. We also show how simple software tools can be used to acquire knowledge about the system, run code in a reproducible way, and validate hypotheses about resource consumption. Finally, once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of code changes can often be predicted, replacing hope-for-the-best optimizations by a scientific process.

This course provides - via lectures, demos, and hands-on labs - scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.



Online course
Organizer: HLRS, University of Stuttgart, Germany


28. Jun 2022


01. Jul 2022






Performance-Optimierung & Debugging

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Prerequisites and content levels

  • Familiarity with Linux and Linux editors is recommended.
  • Basics/principles of programming in C or Fortran and basic OpeMP.
Content levels:
  • Intermediate: 8 hours 15 minutes
  • Advanced: 8 hours 15 minutes
  • Community: 2 hours 45 minutes

Learn more about course curricula and content levels.


Dr. habil. Georg Hager and Dr.-Ing. Jan Eitzinger (formerly Treibig) (RRZE/HPC, Uni. Erlangen)
Bert Wesarg (ZIH Uni. Dresden) for the tools-day


Day 1

  • 08:45   Enter the Zoom meeting
  • 09:00   Welcome – Intro
  • 09:30   Computer architecture for software developers part 1
  • 10:00   Coffee break
  • 10:15   Computer architecture for software developers part 1 cont.
  • 10:45   Hands-on: Warmup (login etc.)
  • 11:00   Computer architecture for software developers part 2
  • 11:45   Hands-on: Divide benchmark
  • 12:30   Lunch
  • 13:30   Tools: Topology and affinity, frequency
  • 14:00   Hands-on: likwid-topology and likwid-pin
  • 14:15   Roofline Model: Basics
  • 15:15   Hands-on: Microarchitectural exploration

Day 2

  • 08:45   Enter the Zoom meeting
  • 09:00   Tools: Performance counters
  • 09:30   Hands-on: performance counters and memory bandwidth
  • 10:00   Optimal use of parallel resources: SIMD
  • 11:00   Coffee break
  • 11:15   Hands-on: SIMD in MiniMD
  • 12:15   Optimal use of parallel resources:  ccNUMA
  • 13:00   Lunch
  • 14:00   Performance Engineering: Basic skills
  • 14:45   Coffee break
  • 15:00   Hands-on: Dense Matrix Vector Multiplication
  • 16:00-   Open end

Day 3

  • 08:45   Enter the Zoom meeting
  • 09:00   Roofline case study: Jacobi smoother
  • 10:00   Coffee break
  • 10:15   Hands-on: Matrix free CG solver part 1
  • 11:15   Coffee break
  • 11:30   Roofline case study: SpMVM
  • 12:30   Lunch
  • 13:30   ECM Performance model
  • 14:15   Coffee break
  • 14:30   Hands-on: Matrix free CG solver part 2 (optimizatons)
  • 16:00   Farewell & feedback

Day 4 (Tools Day)

  • 08:45   Enter the Zoom meeting
  • 09:00   Performance engineering from the application point of view
  • 09:30   Monitoring with Score-P
  • 09:45   Hands-on: MiniMD with Score-P
  • 10:15   Coffee break
  • 10:30   Profile exploration and measurement scoring
  • 10:45   Trace exploration with Vampir
  • 11:15   Coffee break
  • 11:30   Hands-on: Load imbalance: SpMV
  • 12:15   Wrap-up


Detailed Program


  • Our approach to performance engineering
  • Basic architecture of multicore systems: threads, cores, caches, sockets, memory
  • The important role of system topology

Tools topology & affinity in multicore environments

  • Overview
  • likwid-topology and likwid-pin

Microbenchmarking for architectural exploration

  • Properties of data paths in the memory hierarchy
  • Bottlenecks
  • OpenMP barrier overhead

Roofline model: basics

  • Model assumptions and construction
  • Simple examples
  • Limitations of the Roofline model

Tools: hardware performance counters

  • Why hardware performance counters?
  • likwid-perfctr
  • Validating performance models

Roofline case studies

  • Dense matrix-vector multiplication
  • Sparse matrix-vector multiplication
  • Jacobi (stencil) smoother

Optimal use of parallel resources

  • Single Instruction Multiple Data (SIMD)
  • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
  • Simultaneous Multi-Threading (SMT)

Extending Roofline: The ECM performance model

Optional: Pattern-based performance engineering 


Before the course, the course material and an updated agenda will be available here.

An older version of this course with most of the material (including the audio information) can also be viewed in the ONLINE Parallel Programming Workshop.

Registration information

Register via the button at the top of this page.
We encourage you to register to the waiting list if the course is full. Places might become available.

Registration closes on June 12, 2022 (extended deadline).

Late registrations after the deadline are still possible according to the course capacity, maybe with reduced quality of the service.


Students without Diploma/Master: None
Members of German universities and public research institutes: none.
Members of universities and public research institutes within EU or PRACE member countries: none.   
Members of other universities and public research institutes: 240 EUR.
Others: 600 EUR.

Our course fees includes coffee breaks (in classroom courses only).


Lucienne Dettki, phone 0711 685 63894, dettki(at)


HLRS is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in Feb. 2012.

This course is a PATC course, see also the PRACE Training Portal and Events. For participants from public research institutions in PRACE countries, the course fee is sponsored through the PRACE PATC program.

HLRS is also member of the Baden-Württemberg initiative bwHPC.

This course is also provided within the framework of the bwHPC training program.

Further courses

See the training overview and the Supercomputing Academy pages.